HD6417727BP160CV Datasheet, PDF (774/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 23 USB Function Controller
23.6.6 EP3 Interrupt-In Transfer
USB function
IN token reception
Application
Valid data
in EP3 FIFO?
Yes
No
NACK
Data transmission to host
ACK
Clear EP3 transfer-request
flag
(USBIFR1/EP3 TR = 0)
Write data to USBEP3
data register
Write to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
Set EP3 transfer-end flag
(USBIFR1/EP3 TS = 1)
Clear EP3 transfer-end flag
(USBIFR1/EP3 TS = 0)
IN token reception
Write data to USBEP3
data register
Write to EP3 packet
enable bit
(USBTRG/EP3 PKTE = 1)
Note:
This flow is an example of interrupt transfer processing. When there is data to be transferred, the
following flow can also be considered.
"Confirm that FIFO is empty by referring to the EP3 DE bit of the USB data status register and write
data to FIFO."
Figure 23.12 EP2 Interrupt-In Transfer Operation
Rev.6.00 Mar. 27, 2009 Page 716 of 1036
REJ09B0254-0600