HD6417727BP160CV Datasheet, PDF (371/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Bit 0—Refresh Count Overflow Limit Select (LMTS): Indicates the count limit value to be
compared to the number of refreshes indicated in the refresh count register (RFCR). When the
value RFCR overflows the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS
0
1
Description
Count limit value is 1024
Count limit value is 512
(Initial value)
12.2.9 Refresh Timer Counter (RTCNT)
RTCNT is a 16-bit read/write register. RTCNT is an 8-bit counter that counts up with input
clocks. The clock select bits (CKS2 to CKS0) of RTCSR select the input clock. When RTCNT
matches RTCOR, the CMF bit of TCSR is set and RTCNT is cleared. RTCNT is initialized to
H'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized by
standby mode and holds its values unchanged.
Note:
Writing to the RTCNT differs from that to general registers to ensure the RTCNT is not
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions
on Accessing Refresh Control Related Registers.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W
Rev.6.00 Mar. 27, 2009 Page 313 of 1036
REJ09B0254-0600