HD6417727BP160CV Datasheet, PDF (394/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number
of cycles from READ and READA command output cycles Tc1 to Tc4 to the first read data latch
cycle, Td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of A2W1
and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of
synchronous DRAM CAS latency cycles.
Tr
CKIO,
CKIO2
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31 to D0
Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4
Tpc
BS
Figure 12.13 Basic Timing for Synchronous DRAM Burst Read
Figure 12.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10,
and TPC is set to 1.
The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal access space, is
asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle. When a burst read is
performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16
bytes, address updating is performed for A3 and A2 only. The order of access is as follows: in a
Rev.6.00 Mar. 27, 2009 Page 336 of 1036
REJ09B0254-0600