HD6417727BP160CV Datasheet, PDF (468/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
SAR3
D
DAR3
M
A _Temporary
C
buffer
Data
buffer
Memory
Transfer source module
Transfer destination
module
Data is read from memory using the SAR3 value as the data address, and the read
data is stored in the temporary buffer. The read data must be a 32-bit value because it
is used as an address.
Two bus cycles are required if a 16-bit data bus is used to connect to an external
device.
First and second bus cycles
SAR3
D
DAR3
M
A _Temporary
C
buffer
Data
buffer
Memory
Transfer source module
Transfer destination
module
Data is read from the source module using the temporary buffer value as the address,
and the read data is transferred to the data buffer.
Third bus cycle
SAR3
D
DAR3
M
A _Temporary
C
buffer
Data
buffer
Memory
Transfer source module
Transfer destination
module
The data buffer value is written to the destination module using the DAR3 value as the
destination address.
Fourth bus cycle
Note: The above description uses the memory, transfer source module, or transfer
destination module; in practice, any module can be connected in the addressing
space.
Figure 14.9 Operation in Indirect Address Mode
(When the External Memory Space is Set to 16-bit Width)
Rev.6.00 Mar. 27, 2009 Page 410 of 1036
REJ09B0254-0600