HD6417727BP160CV Datasheet, PDF (647/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.3 Operation
19.3.1 Overview
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually. Refer to section 17.3.2, Operation in Asynchronous Mode. The SCIF
has the 16-byte FIFO buffer for both transmit and receive, reduces an overhead of the CPU, and
enables continuous high-speed communication. Moreover, it has the RTS2 and CTS2 signals as
the modem control signals. The transmission format is selected in the serial mode register 2
(SCSMR2), as listed in table 19.6. The clock source of SCIF is determined by the combination of
CKE1 and CKE0 bits in the serial control register 2 (SCSCR2) as shown in table 19.7.
• Data length is selectable from seven or eight bits.
• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The
combination of the preceding selections constitutes the communication format and character
length.
• In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO
data full, receive data ready, and breaks.
• In transmitting, it is possible to detect transmit FIFO data empty.
• The number of stored data for both the transmit and receive FIFO registers is displayed.
• SCIF clock source
⎯ The SCIF operates using the on-chip baud rate generator, and can output a serial clock
signal with a frequency 16 times the bit rate.
Table 19.6 SCSMR2 Settings and SCIF Transmit/Receive
Mode
Asynchronous
SCSMR2 Settings
Bit 6
CHR
Bit 5
PE
Bit 3
STOP
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Data
Length
8-bit
7-bit
SCIF Transmit/Receive
Parity
Bit
Stop Bit Length
Not set
1 bit
2 bits
Set
1 bit
2 bits
Not set
1 bit
2 bits
Set
1 bit
2 bits
Rev.6.00 Mar. 27, 2009 Page 589 of 1036
REJ09B0254-0600