HD6417727BP160CV Datasheet, PDF (410/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Memory Card Interface Basic Timing: Figure 12.25 shows the basic timing for the PCMCIA IC
memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface
areas, bus accesses are automatically performed as IC memory card interface accesses.
With a high external bus frequency (CKIO), the setup and hold times for the address (A24 to A0),
card enable (CS5, CE2A, CS6, CE2B), and write data (D15 to D0) in a write cycle, become
insufficient with respect to RD and WR (the WE pin in this LSI). This LSI provides for this by
enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register. Also,
software waits by means of a WCR2 register setting and hardware waits by means of the WAIT
pin can be inserted in the same way as for the basic interface. Figure 12.26 shows the PCMCIA
memory bus wait timing.
Rev.6.00 Mar. 27, 2009 Page 352 of 1036
REJ09B0254-0600