HD6417727BP160CV Datasheet, PDF (512/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 15 Timer (TMU)
15.4.2 Status Flag Clear Timing
The status flag is cleared when 0 is written by the CPU. Figure 15.7 shows the timing.
TCR write cycle
T1
T2
T3
Pφ
Peripheral address bus
TCR address
UNF
Figure 15.7 Status Flag Clear Timing
15.4.3 Interrupt Sources and Priorities
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the corresponding interrupt is requested. When an interrupt is
generated, codes are set in the interrupt event register (INTEVT, INTEVT2). Provide the
appropriate interrupt handling according to the codes.
The channel priority can be changed using the interrupt controller (see section 4, Exception
Handling, and section 7, Interrupt Controller (INTC)). Table 15.2 lists TMU interrupt sources.
Table 15.2 TMU Interrupt Sources
Channel
0
1
2
Interrupt Source
TUNI0
TUNI1
TUNI2
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Priority
High
Low
Rev.6.00 Mar. 27, 2009 Page 454 of 1036
REJ09B0254-0600