HD6417727BP160CV Datasheet, PDF (475/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority Order: For example, when channel 1 provides transfer
operation in burst mode and then a transfer request to channel 0 with the higher priority is
generated, the transfer of channel 0 will begin immediately.
At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will be
continued after the channel 0 transfer has completely finished, even if channel 0 is set to the cycle
steal mode or burst mode.
If the round-robin mode is selected, channel 1 will begin operating again after channel 0 completes
the transfer of one transfer unit, even if channel 0 is set to the cycle steal mode or burst mode. The
bus is moved between the two in the order channel 1, channel 0, channel 1, channel 0.
Even if the fixed mode or in the round-robin mode is selected, the bus is not passed to the CPU
since channel 1 is in the burst mode. Figure 14.16 shows an example of operation in the round-
robin mode.
CPU
DMAC
CH1
DMAC
CH1
DMAC
CH0
CH0
DMAC
CH1
CH1
DMAC
CH0
CH0
DMAC
CH1
DMAC
CH1
CPU
CPU
DMAC CH1
Burst mode
Round-robin mode in
DMAC CH0 and CH1
DMAC CH1
Burst mode
CPU
Priority: Round-robin mode
CH0: Cycle-steal mode
CH1: Burst mode
Figure 14.16 Bus State in Multiple Channel Operation
Rev.6.00 Mar. 27, 2009 Page 417 of 1036
REJ09B0254-0600