HD6417727BP160CV Datasheet, PDF (671/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
Bit 6—Transmit Left Channel Data Repeatedly (TLREP): Setting of this bit is effective when
TDRE bit is 1. When 1 is set to this bit, setting of bits 15 to 0 in SITDR register is ignored.
Bit 6: TLREP
0
1
Description
The data in SITDR bit of SITDR register is transmitted as right channel data.
(Initial value)
The data in SITDL bit of SITDL register is transmitted as right channel data.
Bits 3 to 0—Transmit Data for Right Channel Slot Assignment (TDRA3 to TDRA0): The slot
assignment of transmit data for Right channel in transmit frame is specified from 0000(0: initial
value) to 1110(14) by this register. The transmit data for right channel is set in SITDR bits 15 to 0
in SITDR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits TDRA3 to TDRA0.
20.2.4 Receive Data Assign Register (SIRDAR)
This register specifies the data assignment of received data in each received frame. This register is
initialized at power on reset or software reset.
Bit: 15
14
13
12
11
10
9
8
RDLE
—
—
— RDLA3 RDLA2 RDLA1 RDLA0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
RDRE
—
—
— RDRA3 RDRA2 RDRA1 RDRA0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R/W
R/W
R/W
R/W
Bits 14 to 12, and 6 to 4—Reserved
Bit 15—Receive Data for Left Channel Enable (RDLE)
Bit 15: RDLE
0
1
Description
Disable receiving of left channel data
Enable receiving of left channel data
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 613 of 1036
REJ09B0254-0600