HD6417727BP160CV Datasheet, PDF (191/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 4 Exception Handling
Table 4.2 Exception Event Vectors
Exception
Type
Reset
General
exception
events
Current
Instruction
Aborted
Aborted
and retried
Completed
Exception Event
Priority^*1
Power-on reset
1
Manual reset
1
H-UDI reset
1
CPU address error 2
(instruction access)
TLB miss
2
(instruction access
not in repeat loop)
TLB miss
2
(instruction access in
repeat loop)^*4
TLB invalid
2
(instruction access)
TLB protection
2
violation
(instruction access)
General illegal
2
instruction exception
Illegal slot instruction 2
exception
CPU address error 2
(data access)
TLB miss
2
(data access not in
repeat loop)
TLB miss
2
(data access in repeat
loop)^*4
TLB invalid (data
2
access)
TLB protection
2
violation
(data access)
Initial page write
2
Unconditional trap
2
(TRAPA instruction)
User breakpoint trap 2
DMA address error 2
Exception
Order
—
—
—
1
2
2
3
4
5
5
6
7
7
8
9
10
5
n^*2
12
Vector
Address
H'A0000000
H'A0000000
H’A0000000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Vector Offset
—
—
—
H'00000100
H'00000400
H’00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
Rev.6.00 Mar. 27, 2009 Page 133 of 1036
REJ09B0254-0600