HD6417727BP160CV Datasheet, PDF (602/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 18 Smart Card Interface
18.1.2 Block Diagram
Figure 18.1 shows a block diagram of the smart card interface.
Module data bus
RxD0
TxD0
SCK0
SCRDR
SCRSR
SCTDR
SCTSR
SCSCMR
SCSSR
SCSCR
SCSMR
Transmit/
receive
control
SCBRR
Baud rate
generator
Parity generation
Parity check
Clock
External clock
SCI
Legend:
SCSCMR: Smart card mode register
SCRSR: Receive shift register
SCRDR: Receive data register
SCTSR: Transmit shift register
SCTDR: Transmit data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCSSR: Serial status register
SCBRR: Bit rate register
Figure 18.1 Smart Card Interface Block Diagram
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXI
RXI
ERI
Rev.6.00 Mar. 27, 2009 Page 544 of 1036
REJ09B0254-0600