HD6417727BP160CV Datasheet, PDF (223/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 7 Interrupt Controller (INTC)
Section 7 Interrupt Controller (INTC)
7.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
7.1.1 Features
INTC has the following features:
• 16 levels of interrupt priority can be set: By setting the five interrupt-priority registers, the
priorities of on-chip supporting module, IRQ, and PINT interrupts can be selected from 16
levels for individual request sources.
• NMI noise canceller function: NMI input-level bit indicates NMI pin states. By reading this bit
in the interrupt exception service routine, the pin state can be checked, enabling it to be used as
a noise canceller.
Rev.6.00 Mar. 27, 2009 Page 165 of 1036
REJ09B0254-0600