HD6417727BP160CV Datasheet, PDF (240/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 7 Interrupt Controller (INTC)
Bit 13: BLMSK Description
0
NMI interrupts are masked when the BL bit is 1
1
NMI interrupts are accepted regardless of the BL bit setting
(Initial value)
Bit 12—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 11 and 10—IRQ5 Sense Select (IRQ51S and IRQ50S): Select whether the interrupt signal
to the IRQ5 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 11: IRQ51S Bit 10: IRQ50S Description
0
0
An interrupt request is detected at IRQ5 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ5 input rising edge
1
0
An interrupt request is detected at IRQ5 input low level
1
Reserved
Bits 9 and 8—IRQ4 Sense Select (IRQ41S and IRQ40S): Select whether the interrupt signal to
the IRQ4 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 9: IRQ41S
0
1
Bit 8: IRQ40S
0
1
0
1
Description
An interrupt request is detected at IRQ4 input falling edge
(Initial value)
An interrupt request is detected at IRQ4 input rising edge
An interrupt request is detected at IRQ4 input low level
Reserved
Bits 7 and 6—IRQ3 Sense Select (IRQ31S and IRQ30S): Select whether the interrupt signal to
the IRQ3 pin is detected at the rising edge, at the falling edge, or at low level.
Bit 7: IRQ31S
0
1
Bit 6: IRQ30S
0
1
0
1
Description
An interrupt request is detected at IRQ3 input falling edge
(Initial value)
An interrupt request is detected at IRQ3 input rising edge
An interrupt request is detected at IRQ3 input low level
Reserved
Rev.6.00 Mar. 27, 2009 Page 182 of 1036
REJ09B0254-0600