HD6417727BP160CV Datasheet, PDF (466/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
CKIO
A25 to A0 _{Transfer +4}
+8
source address
CSn
D31 to D0
RD
WEm
DACK
Data read cycle
+12
Transfer +4
destination address
+8
+12
(1st cycle)
(2nd cycle)
Note: When DACK is output in a read cycle during transfer between external memories,
the output timing is the same as that of CSn.
Figure 14.7 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary
Memory)
CKIO
A25 to A0
CSn
D31 to D0
RAS
CAS
RD/WR
DACK
Transfer source address Transfer destination address +4
+8
+12
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: When DACK is output in a read cycle during transfer between external memories,
the output timing is the same as that of CSn.
Figure 14.8 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary
Memory)
Rev.6.00 Mar. 27, 2009 Page 408 of 1036
REJ09B0254-0600