HD6417727BP160CV Datasheet, PDF (777/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 23 USB Function Controller
(1) Transition from normal operation to stall
(1-1)
USB
Internal status bit
0
USBEPSTL
0→1
1. 1 written to
USBEPSTL by
application
(1-2)
Transaction request
Reference
Internal status bit
0
USBEPSTL
1
(1-3)
STALL handshake
Stall
Internal status bit
0→1
USBEPSTL
1
To (2-1) or (3-1)
(2) When Clear Feature is sent after USBEPSTL is cleared
(2-1)
Transaction request
Internal status bit
1
USBEPSTL
1→0
(2-2)
STALL handshake
Internal status bit
1
USBEPSTL
0
1. IN/OUT token
received from host
2. USBEPSTL
referenced
1. 1 set in USBEPSTL
2. Internal status bit
set to 1
3. Transmission of
STALL handshake
1. USBEPSTL cleared
to 0 by application
2. IN/OUT token
received from host
3. Internal status bit
already set to 1
4. USBEPSTL not
referenced
5. Internal status bit
not changed
1. Transmission of
STALL handshake
(2-3)
Clear Feature command
Internal status bit
1→0
USBEPSTL
0
1. Internal status bit
cleared to 0
Normal status restored
(3) When Clear Feature is sent before USBEPSTL is cleared to 0
(3-1)
Clear Feature command
Internal status bit
1→0
USBEPSTL
1
To (1-2)
1. Internal status bit
cleared to 0
2. USBEPSTL not
changed
Figure 23.13 Forcible Stall by Application
Rev.6.00 Mar. 27, 2009 Page 719 of 1036
REJ09B0254-0600