HD6417727BP160CV Datasheet, PDF (323/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Clock Mode FRQCR
7
H'0100
H'0101
H'0102
H'0111
H'0112
H'0115
H'0116
H'0122
H'0126
H'012A
H'A100
H'A101
H'E100
H'E101
H'A111
Note: * Taking input clock as 1
PLL1
ON (× 1)
ON (× 1)
ON (× 1)
ON (× 2)
ON (× 2)
ON (× 2)
ON (× 2)
ON (× 4)
ON (× 4)
ON (× 4)
ON (× 3)
ON (× 3)
ON (× 3)
ON (× 3)
ON (× 6)
Section 10 On-Chip Oscillation Circuits
PLL2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Clock Rate* (I:B:P)
1:1:1
1:1:1/2
1:1:1/4
2:1:1
2:1:1/2
1:1:1
1:1:1/2
4:1:1
2:1:1
1:1:1
3:1:1
3:1:1/2
1:1:1
1:1:1/2
6:1:1
Cautions:
1. The frequency ranges of the input clock and crystal resonator should be set within the specified
frequency range based on the clock rate in table 10.4, and section 32.3, AC Characteristics.
2. The input to divider 1 becomes the output of PLL circuit 1 when PLL circuit 1 is on.
3. The input of divider 2 becomes the output of:
• PLL circuit 1
4. The frequency of the internal clock (Iφ) becomes:
• The product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL
circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on.
• Do not set the internal clock frequency lower than the CKIO pin frequency.
• Depending on the product, the clock ratio should be set to produce a frequency within one
of the ranges indicated below.
100 MHz products: 24 MHz to 100 MHz
160 MHz products: 24 MHz to 160 MHz
Rev.6.00 Mar. 27, 2009 Page 265 of 1036
REJ09B0254-0600