TCI6636K2H Datasheet, PDF (98/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 6-7
Privilege ID Settings (Part 2 of 2)
Privilege ID Master
Privilege Level
Security Level
5
C66x CorePac5
SW dependent, driven by MSMC
Non-secure
6
C66x CorePac6
SW dependent, driven by MSMC
Non-secure
7
C66x CorePac7
SW dependent, driven by MSMC
Non-secure
8
ARM CorePac
SW dependent
Non-secure
9
SRIO_M and all Packet DMA masters (NetCP, User/driven by SRIO block, user mode and
Non-secure
Both QM_CDMA, FFTC, BCP_CDMA, AIF,
supervisor mode is determined by per transaction
SRIO_CDMA, USB
basis. Only the transaction with source ID matching
the value in SupervisorID register is granted
supervisor mode.
10
QM_Second ⁽¹⁾
User
Non-secure
11
PCIe
Supervisor
Non-secure
12
DAP
Driven by Emulation SW
Non-secure
13
RAC_TAC/BCP_DIO
Supervisor
Non-secure
14
HyperLink
Supervisor
Non-secure
15
Reserved
End of Table 6-7
1 QM_Second provides a path that PDSP uses to access the system memory.
Access Type
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
6.2.1 MPU Registers
This section includes the offsets for MPU registers and definitions for device-specific MPU registers. For Number
of Programmable Ranges supported (PROGx_MPSA, PROGxMPEA) refer to the following tables.
6.2.1.1 MPU Register Map
Table 6-8
Offset
0h
4h
10h
14h
18h
1Ch
20h
200h
204h
208h
210h
214h
218h
220h
224h
228h
230h
234h
238h
MPU Registers (Part 1 of 2)
Name
REVID
CONFIG
IRAWSTAT
IENSTAT
IENSET
IENCLR
EOI
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPAR
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPAR
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPAR
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPAR
Description
Revision ID
Configuration
Interrupt raw status/set
Interrupt enable status/clear
Interrupt enable
Interrupt enable clear
End of interrupt
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
98 Memory, Interrupts, and EDMA for TCI6636K2H
Copyright 2013 Texas Instruments Incorporated
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