TCI6636K2H Datasheet, PDF (32/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
4.5 Main TeraNet Connection
There is one master port coming out of the ARM CorePac. The master port is a 256 bit wide port for the transactions
going to the MSMC and DDR_EMIF data spaces.
4.6 Clocking and Reset
4.6.1 Clocking
The ARM CorePac includes a dedicated embedded DPLL (ARM PLL). The Cortex-A15 processor core clocks are
sourced from this ARM PLL Controller. The Cortex-A15 processor core clock has a maximum frequency of 1.4 Ghz.
The ARM CorePac subsytem also uses the SYSCLK1 clock source from the main PLL is locally divided (/1, /3 and
/6) and provided to certain sub-modules inside the ARM CorePac. AINTC sub module runs at a frequency of
SYSCLK1/6.
4.6.2 Reset
The ARM CorePac does not support local reset. It is reset whenever the device is under reset. In addition, the
interrupt controller (AINTC) can only be reset during POR and RESETFULL. AINTC also resets whenever device
is under reset.
For the complete programming model, refer to the KeyStone II ARM CorePac User Guide.
32 ARM CorePac
Copyright 2013 Texas Instruments Incorporated
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