TCI6636K2H Datasheet, PDF (292/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Figure 10-6 Boot Configuration Timing
POR
1
RESETFULL
GPIO[15:0]
2
10.5 Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL and the PLL Controllers
This section provides a description of the Main PLL, ARM PLL, DDR3A PLL, DDR3B PLL, PASS PLL, and the PLL
Controller. For details on the operation of the PLL Controller module, see the Phase Locked Loop (PLL) Controller
for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
The Main PLL is controlled by the standard PLL Controller. The PLL Controller manages the clock ratios,
alignment, and gating for the system clocks to the device. By default, the device powers up with the main PLL
bypassed. Figure 10-7 shows a block diagram of the Main PLL and the PLL Controller.
The ARM PLL,DDR3A PLL, DDR3B PLL, and PASS PLL are used to provide dedicated clock to the ARM
CorePac,DDR3A, DDR3B, and PASS respectively. These chip level PLLs support a wide range of multiplier and
divider values, which can be programmed through the chip level registers located in the Device Control Register
block. The Boot ROM will program the multiplier values for main PLL, ARM PLLand PASS PLL based on boot
mode. (See ‘‘Device Boot and Configuration’’ on page 207 for more details.)
The DDR3A PLL and DDR3B PLL are used to supply clocks to DDR3A and DDR3B EMIF logic. These PLLs can
also be used without programming the PLL Controller. Instead, they can be controlled using the chip-level registers
(DDR3APLLCTL0, DDR3APLLCTL1,DDR3BPLLCTL0, DDR3BPLLCTL1) located in the Device Control Register
block. To write to these registers, software must go through an unlocking sequence using the KICK0/KICK1
registers.
The multiplier values for all chip-level PLLs can be reprogrammed later based on the input parameter table. This
feature provides flexibility in that these PLLs may be able to reuse other clock sources instead of having its own clock
source.
292 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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