TCI6636K2H Datasheet, PDF (230/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.4.10 DDR3 Configuration Table
The RBL also provides an option to configure the DDR table before loading the image into the external memory.
More information on how to configure the DDR3, refer to the Bootloader User Guide. The configuration table for
DDR3 is shown in Table 8-26
Table 8-26 DDR3 Boot Parameter Table
Byte Offset Name
0
configselect msw
4
configselect slsw
8
configselect lsw
12
pllprediv
16
pllMult
20
pllPostDiv
24
sdRamConfig
28
sdRamConfig2
32
sdRamRefreshctl
36
sdRamTiming1
40
sdRamTiming2
44
sdRamTiming3
48
IpDfrNvmTiming
52
powerMngCtl
56
iODFTTestLogic
60
performcountCfg
64
performCountMstRegSel
68
readIdleCtl
72
sysVbusmIntEnSet
76
sdRamOutImpdedCalcfg
80
tempAlertCfg
84
ddrPhyCtl1
88
ddrPhyCtl2
92
proClassSvceMap
96
mstId2ClsSvce1Map
100
mstId2ClsSvce2Map
104
eccCtl
108
eccRange1
112
eccRange2
116
rdWrtExcThresh
120 - 376 Chip Config
End of Table 8-26
Description
Selecting the configuration register below that to be set. Each filed
below is represented by one bit each.
Selecting the configuration register below that to be set. Each filed
below is represented by one bit each.
Selecting the configuration register below that to be set. Each filed
below is represented by one bit each.
PLL pre divider value (Should be the exact value not value -1)
PLL Multiplier value (Should be the exact value not value -1)
PLL post divider value (Should be the exact value not value -1)
SDRAM config register
SDRAM Config register
SDRAM Refresh Control Register
SDRAM Timing 1 Register
SDRAM Timing 2 Register
SDRAM Timing 3 Register
LP DDR2 NVM Timing Register
Power management Control Register
IODFT Test Logic Global Control Register
Performance Counter Config Register
Performance Counter Master Region Select Register
Read IDLE counter Register
System Interrupt Enable Set Register
SDRAM Output Impedence Calibration Config Register
Temperature Alert Configuration Register
DDR PHY Control Register 1
DDR PHY Control Register 1
Priority to Class of Service mapping Register
Master ID to Class of Service Mapping 1 Register
Master ID to Class of Service Mapping 2Register
ECC Control Register
ECC Address Range1 Register
ECC Address Range2 Register
Read Write Execution Threshold Register
Chip Specific PHY configuration
Configured Through Boot
Configuration Pins
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
230 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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