TCI6636K2H Datasheet, PDF (309/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Figure 10-24 USBCLK Rise and Fall Times
TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
T_C Reference Clock Period
peak-to-peak
Differential
Input Voltage
0
(600 mV to 1700 mV)
10% to 90%
of peak-to-peak
Voltage
Max T_R = TBD _× T_C from
10% to 90% of the
peak-to-peak
Differential Voltage
Max T_F = TBD _× T_C from
90% to 10% of the
peak-to-peak
Differential Voltage
10.6 DDR3A PLL and DDR3B PLL
The DDR3A PLL and DDR3B PLL generate interface clocks for the DDR3A and DDR3B memory controllers. When
coming out of power-on reset, DDR3A PLL and DDR3B PLL are programmed to a valid frequency during the boot
configuration process before being enabled and used.
DDR3A PLL and DDR3B PLL power is supplied via the DDR3 PLL power-supply pin (AVDDA2). An external EMI
filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices (in
development) for detailed recommendations.
Figure 10-25 DDR3A PLL and DDR3B PLL Block Diagram
PLLM
DDR3 PLL
DDRCLK(N|P)
PLLD
VCO
0
CLKOD
1
BYPASS
PLLOUT
DDR3
´2 ^PHY
DDR
10.6.1 DDR3A PLL and DDR3B PLL Control Registers
The DDR3A PLL and DDR3B PLL, which are used to drive the DDR3A PHY and DDR3B PHY for the EMIF, do
not use a PLL controller. DDR3A PLL and DDR3B PLL can be controlled using the
DDR3APLLCTL0/DDR3BPLLCTL0 and DDR3APLLCTL1/DDR3BPLLCTL1 registers located in the Bootcfg
module. These MMRs (memory-mapped registers) exist inside the Bootcfg space. To write to these registers,
software must go through an unlocking sequence using the KICK0 and KICK1 registers. For suggested configurable
values, see 8.1.4 ‘‘System PLL Settings’’ on page 231. See 8.2.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1)
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TCI6636K2H Peripheral Information and Electrical Specifications 309