TCI6636K2H Datasheet, PDF (29/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
4.1 Features
The key features of the Quad Core ARM CorePac are as follows:
• One or more Cortex-A15 processors, each containing:
– Cortex-A15 processor revision R2P4.
– ARM architecture version 7 ISA.
– Multi-issue, out-of-order, superscalar pipeline.
– L1 and L2 instruction and data cache of 32 KB, 2-way, 16 word line with 128 bit interface.
– Integrated L2 cache of 4MB, 16-way, 16 word line, 128-bit interface to L1 along with ECC/parity.
– Includes the NEON media coprocessor (NEON™), which implements the advanced SIMDv2 media
processing architecture and the VFPv4 Vector Floating Point architecture.
– The external interface uses the AXI protocol configured to 128-bit data width.
– Includes the System Trace Macrocell (STM) support for non-invasive debugging.
– Implements the ARMv7 debug with watchpoint and breakpoint registers and 32-bit advanced peripheral
bus (APB) slave interface to CoreSight™ debug systems.
• Interrupt controller
– Supports up to 480 interrupt requests
• Emulation/debug
– Compatible with CoreSight™ architecture
• Clock generation
– Through the dedicated ARM PLL
4.2 System Integration
The ARM CorePac integrates the following group of submodules.
• Cortex™-A15 Processors: Provides a high processing capability, including the NEON™ technology for mobile
multimedia acceleration. The Cortex™-A15 communicates with the rest of the ARM CorePac through an AXI
bus with an AXI2VBUSM bridge and receives interrupts from the ARM CorePac interrupt controller (ARM
INTC).
• Interrupt Controller: Handles interrupts from modules outside of the ARM CorePac (for details, see ‘‘ARM
Interrupt Controller’’).
• Clock Divider: Provides the required divided clocks to the internal modules of the ARM CorePac and has a
clock input from the ARM PLL and the Main PLL
• In-Circuit Emulator: Fully compatible with CoreSight™ architecture and enables debugging capabilities.
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