TCI6636K2H Datasheet, PDF (281/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-6 Power Domains (Part 2 of 2)
Domain Block(s)
29
Reserved
30
ARM Smart Reflex
31
ARM CorePac
End of Table 10-6
Note
Reserved
Logic can be powered down
Logic can be powered down
Power Connection
Reserved
Software control
Software control
10.3.2 Clock Domains
Clock gating to each logic block is managed by the Local Power Sleep Controllers (LPSCs) of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and
disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls
the clock gating logic for each module.
The following table shows the TCI6636K2H clock domains.
Table 10-7 Clock Domains (Part 1 of 2)
LPSC Number
Module(s)
0
Shared LPSC for all peripherals other than those listed in this table
1
Reserved
2
USB
3
EMIF16 and SPI
4
Reserved
5
Debug subsystem and tracers
6
Reserved
7
Packet Accelerator
8
Ethernet SGMIIs
9
Security Accelerator
10
PCIe
11
SRIO
12
HyperLink0
13
SmartReflex
14
MSMC RAM
15
C66x CorePac0
16
C66x CorePac1
17
C66x CorePac2
18
C66x CorePac3
19
C66x CorePac4
20
C66x CorePac5
21
C66x CorePac6
22
C66x CorePac7
23
DDR3A EMIF
24
DDR3B EMIF
25
TAC
26
RAC_0 and RAC_1
27
Reserved
28
FFTC_0
Notes
Always on
Reserved
Software control
Software control
Reserved
Software control
Always on
Software control
Software control
Software control
Software control
Software control
Software control
Always on
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Reserved
Software control
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 281