TCI6636K2H Datasheet, PDF (245/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2.3.10 Power State Control (PWRSTATECTL) Register
The Power State Control Register (PWRSTATECTL) is controlled by the software to indicate the power-saving
mode. Under ROM code, the C66x CorePac reads this register to differentiate between the various power saving
modes. This register is cleared only by POR and is not changed by any other device reset. See the Hardware Design
Guide for KeyStone II Devices (in development) for more information. The PWRSTATECTL Register is shown in
Figure 8-21 and described in Table 8-39.
Figure 8-21 Power State Control Register (PWRSTATECTL)
31
10 9
8
7
6
54
3
2
1
0
Hibernation Recovery Branch Width Wait Recovery Master Local Reset Action Stored Hibernation Mode
Address
SR Index
RW+0000 0000 0000 0000 00 RW+0 RW+0
RW+0
RW+0
RW+0
RW+0
Legend: R = Read Only, RW = Read/Write; -n = value after reset
Hibernation Reserved
RW+0
R+0
Table 8-39 Power State Control Register Field Descriptions
Bit Field
Description
31-10 Hibernation Recovery Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User
Branch Address
Guide in2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
9
Width
EMIF 16 Width (if the recovery address is in EMIF16 space).
0 = 8-bit
1 = 16-bit
8
Wait
Extended Wait (if the recovery address is in EMIF16 space)
0 = Extended Wait disabled
1 = Extended Wait enabled
7
Recovery Master
Master performs hibernation recovery
0 = C66x CorePacs perform hibernation recovery
1 = ARM CorePac performs hibernation recovery
6-5 Local Reset Action
Action of Local Reset
00 = Idle on Local Reset
01 = Branch to the base of MSMC on Local Reset
10 = Branch to the base of DDR3 on Local Reset
11 = Branch to the base of L2 on Local Reset (C66x CorePac)
4-3 Stored Index
0-3 value latched in the SR bits of the DEVSTAT register
2
Hibernation Mode Indicates whether the device is in hibernation mode 1 or mode 2.
0 = Hibernation mode 1
1 = Hibernation mode 2
1
Hibernation
Indicates whether the device is in hibernation mode or not.
0 = Not in hibernation mode
1 = Hibernation mode
0
Reserved
Reserved
End of Table 8-39
Copyright 2013 Texas Instruments Incorporated
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Device Boot and Configuration 245