TCI6636K2H Datasheet, PDF (251/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-45 Timer Input Selection Field Description (Part 3 of 3)
Bit Field
5 TINPHSEL2
4 TINPLSEL2
3 TINPHSEL1
2 TINPLSEL1
1 TINPHSEL0
0 TINPLSEL0
End of Table 8-45
Description
Input select for TIMER2 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER2 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER1 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER1 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER0 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER0 low.
0 = TIMI0
1 = TIMI1
8.2.3.17 Timer Output Selection Register (TOUTPSEL)
The control register TOUTSEL handles the timer output selection and is shown in Figure 8-28 and described in
Table 8-46.
Figure 8-28 Timer Output Selection Register (TOUTPSEL)
31
10 9
54
0
Reserved
TOUTPSEL1
TOUTPSEL0
R-0000000000000000000000
RW-00001
RW-00000
Legend: R = Read only; RW = Read/Write; -n = value after reset
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Device Boot and Configuration 251