TCI6636K2H Datasheet, PDF (181/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 6-36 EDMA3CC2 Events for TCI6636K2H (Part 1 of 2)
Event No. Event Name
Description
0
TAC_DEVT2
TAC debug
1
TAC_DEVT3
TAC debug
2
TAC_DEVT4
TAC debug
3
TAC_DEVT5
TAC debug
4
AIF_ATEVT4
AIF timer
5
AIF_ATEVT5
AIF timer
6
TETB_FULLINT4
TETB4 is full
7
TETB_HFULLINT4
TETB4 is half full
8
TETB_FULLINT5
TETB5 is full
9
TETB_HFULLINT5
TETB5 is half full
10
TETB_FULLINT6
TETB6 is full
11
TETB_HFULLINT6
TETB6 is half full
12
TETB_FULLINT7
TETB7 is full
13
TETB_HFULLINT7
TETB7 is half full
14
SRIO_INTDST0
SRIO interrupt
15
SRIO_INTDST1
SRIO interrupt
16
SRIO_INTDST2
SRIO interrupt
17
SRIO_INTDST3
SRIO interrupt
18
SRIO_INTDST4
SRIO interrupt
19
SRIO_INTDST5
SRIO interrupt
20
SRIO_INTDST6
SRIO interrupt
21
SRIO_INTDST7
SRIO interrupt
22
AIF_ATEVT6
AIF timer
23
AIF_ATEVT7
AIF timer
24
TAC_DEVT0
TAC debug
25
TAC_DEVT1
TAC debug
26
GPIO_INT0
GPIO interrupt
27
GPIO_INT1
GPIO interrupt
28
GPIO_INT2
GPIO interrupt
29
GPIO_INT3
GPIO interrupt
30
GPIO_INT4
GPIO interrupt
31
GPIO_INT5
GPIO interrupt
32
GPIO_INT6
GPIO interrupt
33
GPIO_INT7
GPIO interrupt
34
TCP3D_0_REVT0
TCP3d event
35
TCP3D_0_REVT1
TCP3d event
36
TCP3D_1_REVT0
TCP3d event
37
TCP3D_1_REVT1
TCP3d event
38
CIC_2_OUT48
CIC2 Interrupt Controller output
39
TAC_INT
TAC interrupt
40
UART_0_URXEVT
UART0 receive event
41
UART_0_UTXEVT
UART0 transmit event
42
CIC_2_OUT22
CIC2 Interrupt Controller output
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Memory, Interrupts, and EDMA for TCI6636K2H 181