TCI6636K2H Datasheet, PDF (352/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.36.6 Trace
The device supports trace. Trace is a debug technology that provides a detailed, historical account of application
code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis.
Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for trace advanced emulation, see the Emulation and Trace
Headers Technical Reference in 2.4 ‘‘Related Documentation from Texas Instruments’’ on page 19.
10.36.6.1 Trace Electrical Data/Timing
Table 10-69 Trace Switching Characteristics
(see Figure 10-62)
No.
Parameter
Min Max Unit
1 t_w(DPnH)
Pulse duration, DPn/EMUn high
2.4
ns
1 t_w(DPnH)90% Pulse duration, DPn/EMUn high detected at 90% Voh
1.5
ns
2 t_w(DPnL)
Pulse duration, DPn/EMUn low
2.4
ns
2 t_w(DPnL)10% Pulse duration, DPn/EMUn low detected at 10% Voh
1.5
ns
3 t_sko(DPn)
Output skew time, time delay difference between DPn/EMUn pins configured as trace
-1
1 ns
t_skp(DPn)
Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high (tplh) propagation delays.
600 ps
t_{sldp_o}(DPn) Output slew rate DPn/EMUn
3.3
V/ns
End of Table 10-69
Figure 10-62 Trace Timing
Buffer Buffers
DP[n] /
Inputs
EMU[n] Pins
B
A
C
A
T_PLH
B
C
T_PHL
1
2
3
10.36.7 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) interface is used to support boundary scan and emulation of the device. The
boundary scan supported allows for an asynchronous test reset (TRST) and only the five baseline JTAG signals (e.g.,
no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test
Specification (IEEE1149.1), while all of the SerDes (SRIO and SGMII) support the AC-coupled net test defined in
AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in
accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
352 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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