TCI6636K2H Datasheet, PDF (271/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.2.1 Power-Up Sequencing
This section defines the requirements for a power-up sequencing from a power-on reset condition. There are two
acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO
voltages as shown below.
1. CVDD
2. CVDD1, CVDDT1, VDDAHV, AVDDAx, DVDD18
3. DVDD15
4. VDDALV, VDDUSB, VP, VPTX
5. DVDD33
The second sequence provides compatibility with other TI processors with the IO voltage starting before the core
voltages as shown below.
1. VDDAHV, AVDDAx, DVDD18
2. CVDD
3. CVDD1, CVDDT1
4. DVDD15
5. VDDALV, VDDUSB, VP, VPTX
6. DVDD33
The clock input buffers for SYSCLK, ARMCLK, ALTCORECLK, DDR3ACLK, DDR3BCLK, PASSCLK, and
SRIOSGMIICLK use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a
high-impedance state until CVDDis at a valid voltage level. Driving these clock inputs high before CVDDis valid
could cause damage to the device. Once CVDDis valid, it is acceptable that the P and N legs of these clocks may be
held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To
avoid internal oscillation, the clock inputs should be removed from the high impedance state shortly after CVDDis
present.
If a clock input is not used, it must be held in a static state. To accomplish this, the N leg should be pulled to ground
through a 1-kΩ resistor. The P leg should be tied to CVDD to ensure it will not have any voltage present until
CVDDisactive. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be
driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could
cause damage to the device.
The device initialization is divided into two phases. The first phase consists of the time period from the activation of
the first power supply until the point at which all supplies are active and at a valid voltage level. Either of the
sequencing scenarios described above can be implemented during this phase. The figures below show both the
core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire
power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL
triggers the end of the initialization phase, but both must be inactive for the initialization to complete. POR must
always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to
the clock that is used by the C66x CorePacs. See Figure 10-7 for more details.
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 271