TCI6636K2H Datasheet, PDF (295/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.5.1.2 Local Clock Dividers
The clock signals from the Main PLL Controller are routed to various modules and peripherals on the device. Some
modules and peripherals have one or more internal clock dividers. Other modules and peripherals have no internal
clock dividers, but are grouped together and receive clock signals from a shared local clock divider. Internal and
shared local clock dividers have fixed division ratios. See table Table 10-13.
Table 10-13 Main PLL Controller Module Clock Domains Internal and Shared Local Clock Dividers (Part 1 of 2)
Clock
Module
Internal Clock Divider(s) Shared Local Clock Divider
SYSCLK1 Internal Clock Dividers
Antenna Interface Subsystem 2 (AIF2)
/3, /6
--
ARM CorePac
/1, /3, /3, /6, /6
--
Bit Rate Coprocessor (BCP)
/3
--
C66x DSP CorePacs
/1, /2, /3, /4
--
Chip Interrupt Controllers (CICx)
/6
--
DDR3 Memory Controller A (also receives clocks from the DDR3A_PLL) /2
--
DDR3 Memory Controller B (also receives clocks from the DDR3B_PLL) /3
--
EMIF16
/6
--
Enhanced Viterbi-Decoder Coprocessor (VCP)
/3
--
Fast Fourier Transform Coprocessor (FFTC)
/3
--
SYSCLK1 HyperLink
/2, /3, /6
--
Multicore Navigator Queue Manager
/3
--
MultiCore Shared Memory Controller (MSMC)
/1
--
PCI express (PCIe)
/2, /3, /4, /6
--
Receive Accelerator Coprocessor (RAC)
/3, /4
--
ROM
/6
--
Serial Gigabit Media Independent Interface (SGMII)
/2, /3, /6, /8
--
Transmit Accelerator Coprocessor (TAC)
/3
--
Turbo Decoder Coprocessor (TCP3d)
/2, /3
--
Universal Asynchronous Receiver/Transmitter (UART)
/6
--
Universal Serial Bus 3.0 (USB 3.0)
/3, /6
--
SYSCLK1 Shared Local Clock Dividers
Power/Sleep Controller (PSC)
--
/12, /24
EDMA
SYSCLK1
Memory Protection Units (MPUx)
Semaphore
--
/3
TeraNet (SYSCLK1/3 domain)
Boot Config
General-Purpose Input/Output (GPIO)
I²C
SYSCLK1
Security Manager
Serial Peripheral Interconnect (SPI)
--
/6
TeraNet (CPU /6 domain)
Timers
Universal Subscriber Identity Module (USIM)
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TCI6636K2H Peripheral Information and Electrical Specifications 295