TCI6636K2H Datasheet, PDF (228/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.1.2.4.7 HyperLink Boot Parameter Table
Table 8-23 HyperLink Boot Parameter Table
Byte Offset Name
12
Options
14
Number of Lanes
16
SerDes cfg msw
18
SerDes cfg lsw
20
SerDes CFG RX lane 0 cfg msw
22
SerDes CFG RXlane 0 cfg lsw
24
SerDes CFG TX lane 0 cfg msw
26
SerDes CFG TXlane 0 cfg lsw
28
SerDes CFG RX lane 1 cfg msw
30
SerDes CFG RXlane 1 cfg lsw
32
SerDes CFG TX lane 1 cfg msw
34
SerDes CFG TXlane 1 cfg lsw
36
SerDes CFG RX lane 2 cfg msw
38
SerDes CFG RXlane 2 cfg lsw
40
SerDes CFG TX lane 2 cfg msw
42
SerDes CFG TXlane 2 cfg lsw
44
SerDes CFG RX lane 3 cfg msw
46
SerDes CFG RXlane 3 cfg lsw
SerDes CFG TX lane 3 cfg msw
SerDes CFG TXlane 3 cfg lsw
End of Table 8-23
Description
Bits 00 Reserved
Bits 01 Configuration of Hyperlink
0 = HyperLink is configured by RBL
1 = HyperLink is not configured by RBL
Bits 15- 02 = Reserved
Number of Lanes to be configured
PCIe SerDes config word, MSW
PCIe SerDes config word, LSW
SerDes RX lane config word, msw lane 0
SerDes RX lane config word, lsw, lane 0
SerDes TX lane config word, msw lane 0
SerDes TX lane config word, lsw, lane 0
SerDes RX lane config word, msw lane 1
SerDes RX lane config word, lsw, lane 1
SerDes TX lane config word, msw lane 1
SerDes TX lane config word, lsw, lane 1
SerDes RX lane config word, msw lane 2
SerDes RX lane config word, lsw, lane 2
SerDes TX lane config word, msw lane 2
SerDes TX lane config word, lsw, lane 2
SerDes RX lane config word, msw lane 3
SerDes RX lane config word, lsw, lane 3
SerDes TX lane config word, msw lane 3
SerDes TX lane config word, lsw, lane 3
8.1.2.4.8 UART Boot Parameter Table
Table 8-24 UART Boot Parameter Table (Part 1 of 2)
Byte Offset Name
22
Reserved
24
Data Format
26
Protocol
28
Initial NACK Count
30
Max Err Count
32
NACK Timeout
34
Character Timeout
Description
None
Bits 00 Data Format
0 = Data Format is BLOB
1 = Data Format is Boot Table
Bits 15 - 01 Reserved
Bits 00 Protocol
0 = Xmodem Protocol
1 = Reserved
Bits 15 - 01 Reserved
Number of NACK pings to be sent before giving up
Maximum number of consecutive receive errors acceptable.
Time (msecs) waiting for NACK/ACK.
Time Period between characters
Configured Through
Boot Configuration Pins
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
Configured Through Boot
Configuration Pins
NA
NO
NO
NO
NO
NO
NO
228 Device Boot and Configuration
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