TCI6636K2H Datasheet, PDF (265/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-61 USB_PHY_CTL5 Register Field Descriptions
Bit
31-21
20
Field
Reserved
PHY_REF_CLKDIV2
19-13 PHY_MPLL_MULTIPLIER[6:0]
12-4 PHY_SSC_REF_CLK_SEL
3
Reserved
2-0
PHY_SSC_RANGE
End of Table 8-61
Description
Reserved
Input Reference Clock Divider Control.
If the input reference clock frequency is greater than 100 MHz, this signal must be asserted. The
reference clock frequency is then divided by 2 to keep it in the range required by the MPLL.
When this input is asserted, the ref_ana_usb2_clk (if used) frequency will be the reference clock
frequency divided by 4.
MPLL Frequency Multiplier Control.
Multiplies the reference clock to a frequency suitable for intended operating speed.
Spread Spectrum Reference Clock Shifting.
Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input
corresponds to frequency-synthesis coefficient.
. ssc_ref_clk_sel[8:6] = modulous - 1
. ssc_ref_clk_sel[5:0] = 2's complement push amount.
Reserved
Spread Spectrum Clock Range.
Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the
high-speed transmit clocks. Applies a fixed offset to the phase accumulator.
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