TCI6636K2H Datasheet, PDF (4/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
1.6 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
Figure 1-1 Functional Block Diagram
Memory Subsystem
72-Bit
DDR3 EMIF
72-Bit
DDR3 EMIF
Debug & Trace
6MB
MSM
SRAM
MSMC
RRRSRSRSRASRASRASASASAAA RRRSRSRSRASRASRASASASAAA
TCI6636K2H
CCCCCCCCoCCoCCoC6Co6Cor6Cor6o6r6eo6r6e6r6e6r6ex6rPex6rPex6Pex6P™exP™xaP™xaP™xaP™a™ca™ca™cacacccc _{13P13P103P2-103P2-10C23P2K-10C23P2K-10C23P42K-1a0C23P4B2K-a0C24B2KK-a0cC24B2KK-acC24BKKacC2LhB4BKKacLhB4BKacLhB4BK1eacLhBBK1ecLLhBK1ecLLhB1eDL3LhB21eDL3LhB21eDL3221e-DL3221eC-DLC32K2C-DLC32K2C-DC32K2aC-aDC3B2K2aC-aCB2KacC-acCB2KacC-acCBKacChacCLhBKachacLhBachacLehB1aechacLehB1echcLeh1echcLeh1ehLeh1ehLeh1ee1ee1e}
Boot ROM
8´
32KB L1 32KB L1 32KB L1 32KB L1
Semaphore
P-Cache D-Cache P-Cache D-Cache
ARM
ARM
Power
Management
A15
A15
4MB L2 Cache
PLL
5´
EDMA
5´
ARM
ARM
A15
A15
32KB L1 32KB L1 32KB L1 32KB L1
P-Cache D-Cache P-Cache D-Cache
8 C66x DSP Cores @ up to 1.2 GHz
4 ARM Cores @ up to 1.4 GHz
2´ HyperLink
TeraNet
Coprocessors
RAC
2´
TAC
VCP2
4´
TCP3d
2´
FFTC
4´
BCP
Multicore Navigator
Queue _Packet
Manager _DMA
5-Port
Ethernet
Switch
Security
Accelerator
Packet
Accelerator
Network
Coprocessor
4 TCI6636K2H Features and Description
Copyright 2013 Texas Instruments Incorporated
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