TCI6636K2H Datasheet, PDF (1/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
SPRS835F—February 2012—Revised October 2013
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
1 TCI6636K2H Features and Description
1.1 Features
• Eight TMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each With
– 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point DSP Core
› 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
› 19.2 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per CorePac
› 32K Byte L1D Per CorePac
› 1024K Byte Local L2 Per CorePac
• ARM CorePac
– Four ARM® Cortex™-A15 MPCore™ Processors at Up To
1.4 GHz
– 4MB L2 Cache Memory Shared by Four ARM Cores
– Full Implementation of ARMv7-A Architecture
Instruction Set
– 32KB L1 Instruction and Data Caches per Core
– AMBA 4.0 AXI Coherency Extension (ACE) Master Port,
Connected to MSMC for Low Latency Access to Shared
MSMC SRAM
• Multicore Shared Memory Controller (MSMC)
– 6 MB MSM SRAM Memory Shared by Eight DSP CorePacs
and One ARM CorePac
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Hardware Coprocessors
– Two Turbo Decoders
› Supports WCDMA/HSPA/HSPA+/TD-SCDMA, LTE,
LTE-A and WiMAX
› Supports Up To 265 Mbps for LTE at Block Size 6144,
8 Iterations and Up To 200 Mbps for WCDMA at Block
Size 5114, 8 Iterations
› Low DSP Overhead – HW Interleaver Table
Generation and CRC Check
– Four Viterbi Decoders
› Supports Up To 48 Mbps (Length 9, Rate 1/2, Block
Size 6000)
– Two WCDMA Receive Acceleration Coprocessors
› Supports Up To 4096 Correlators
– WCDMA Transmit Acceleration Coprocessor
› Supports Up To 2304 Spreaders
– Four Fast Fourier Transform Coprocessors
› Support Up To 600 Mscps/FFTC at FFT Size 1024
– Bit Rate Coprocessor
› WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A and WiMAX
Uplink and Downlink Bit Processing
› Includes Encoding, Rate Matching/Dematching,
Segmentation, Multiplexing, and More
› Supports Up To DL 1525 Mbps and UL 1030 (on-chip)
or 680 (DDR3) Mbsp for LTE and DL 784 Mbps and UL
395 Mbsp for WCDMA/TD-SCDMA
• Multicore Navigator
– 16k Multi-Purpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire Speed at 1.5 MPackets Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP and WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,
GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,
SHA-2 (256-bit Hash), MD5
› Up To 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
– Ethernet Subsystem
› Five-Port Switch (four SGMII ports)
• Sixteen Rake/Search Accelerators (RSA) for
– Chip Rate Processing for WCDMA Rel'99, HSDPA, and
HSDPA+
– Reed-Muller Decoding
• Peripherals
– Six-Lane SerDes-Based Antenna Interface (AIF2)
› Operating at Up To 6.144 Gbps
› Compliant with OBSAI RP3 and CPRI Standards for 3G
/ 4G (WCDMA, LTE TDD, LTE FDD, TD-SCDMA, and
WiMAX)
– Four Lanes of SRIO 2.1
› Supports Up To 5 GBaud
› Supports Direct I/O, Message Passing
– Two Lanes PCIe Gen2
› Supports Up To 5 GBaud
– Two HyperLinks
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource Scalability
› Supports Up To 50 GBaud
– Five Enhanced Direct Memory Access (EDMA) Modules
– Two 72-Bit DDR3 Interfaces with Speeds Up To 1600
MHz
– EMIF16 Interface
– USB 3.0
– USIM Interface
– Two UART Interfaces
– Three I²C Interfaces
– 32 GPIO Pins
– Three SPI Interfaces
– Semaphore Module
– Twenty 64-Bit Timers
– Five On-Chip PLLs
• Commercial Case Temperature:
– 0°C to 100°C
• Extended Case Temperature:
– - 40°C to 100°C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.