TCI6636K2H Datasheet, PDF (258/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-54 System Endian Status Register Descriptions
Bit Field
31-1 Reserved
0
SYSENDSTAT
End of Table 8-54
Description
Reserved
Reflects the same value as the LENDIAN bit in the DEVSTAT register.
0 - C66x/System is in Big Endian
1 - C66x/System is in Little Endian
8.2.3.26 SYNECLK_PINCTL Register
This register controls the routing of recovered clock signals from any Ethernet port (SGMII of the multiport
switches) to the two clock outputs TSRXCLKOUT0/TSRXCLKOUT1.
Figure 8-37 SYNECLK_PINCTL Register
31
Reserved
R-0000 0000 0000 0000 0000 0000 0
Legend: RW = Read/Write; -n = value after reset
76
4
3
TSRXCLKOUT1SEL
Reserved
RW-0
2
0
TSRXCLKOUT0SEL
RW-0
Table 8-55 SYNECLK_PINCTL Register Descriptions
Bit Field
31-7 Reserved
6-4 TSRXCLKOUT1SEL
3
Reserved
2-0 TSRXCLKOUT0SEL
End of Table 8-55
Description
000 = SGMII Lane 0 rxbclk
001 = SGMII Lane 1 rxbclk
010 = SGMII Lane 2 rxbclk
011 = SGMII Lane 3 rxbclk
100 = Reserved. Do not write.
101 = Reserved. Do not write.
110 = Reserved. Do not write.
111 = Reserved. Do not write.
000 = SGMII Lane 0 rxbclk
001 = SGMII Lane 1 rxbclk
010 = SGMII Lane 2 rxbclk
011 = SGMII Lane 3 rxbclk
100 = Reserved. Do not write.
101 = Reserved. Do not write.
110 = Reserved. Do not write.
111 = Reserved. Do not write.
8.2.3.27 USB PHY Control (USB_PHY_CTLx) Registers
These registers control the USB PHY.
Figure 8-38
31
USB_PHY_CTL0 Register
Reserved
R-0
258 Device Boot and Configuration
12
11
PHY_RTUNE_ACK
R-0
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