TCI6636K2H Datasheet, PDF (354/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
11 Revision History
Revision F
Updated the performance data (Page 1)
Document reorganization resulted in Device Characteristics moved to new dedicated chapter. (Page 17)
Updated pin maps. (Page 36)
Changed RSV074 through RSV081 to "Reserved - leave unconnected" (Page 56)
In the Device Memory Map Summary table, updated the Tracer entries to be more descriptive. (Page 81)
Corrected Master ID 52, 83, 174-177 (Page 94)
Corrected EDMA3CC3 DBS from 128 bytes to 64 bytes (Page 177)
Clarified that the Packet DMA secondary port priority is set by the QM_PRIORITY bit field in the CHIP_MISC_CTL0 register. (Page 207)
Added the USB PHY registers (Page 259)
Updated values in the Absolute Maximum Ratings table (Page 266)
Updated the footnote on SRVnom and its value (Page 267)
Clocking data in the Main PLL Controller/ARM/SRIO/HyperLink/PCIe/USB Clock Input Timing Requirements table updated (Page 305)
Changed the PLL Control Register BYPASS bit reset value to 1 (Page 309)
Corrected the I²C Switching Characteristics units. (Page 319)
Corrected formula for P in the UART Timing Requirements (Page 325)
Corrected formula for C in the Timers Electrical Timing section (Page 330)
Corrected formula for C in the GPIO Electrical Data/Timing section (Page 333)
Changed the Tc to 23ns (Page 353)
Changed CVDDT pin designations to CVDD, as the two have been tied together internally from PG1.1.
Document reorganization.
First Production Data release.
Revision E
Unreleased
Revision D
Added SRIOSGMIICLK clocking info to the table. (Page 305)
Corrected USBVBUS terminal designation. It is not reserved. (Page 58)
Added the bridge numbers to the Interconnect tables in the System Interconnect chapter (Page 194)
Added the TeraNet drawings to the System Interconnect chapter (Page 190)
Updated the Power-Up Sequence information in the Peripheral Information and Electrical Specifications chapter (Page 271)
Corrected Event (48-80) Names (Page 116)
Changed SerDes field to Reserved as it is not implemented (Page 224)
Corrected Buffer Type (Page 268)
Added DEVSPEED address (Page 241)
Removed PLLLOCK LOCK, STAT and EVAL registers (Page 241)
Removed PLLLOCK STAT and EVAL registers (Page 241)
Changed the power up order of power rails (Page 271)
Changed CPTS_RFTCLK_SEL from three bits to four bits (Page 326)
Updated L3 memory data (Page 28)
Updated L2 memory (Page 27)
Updated memory data for L2 and MSM (Page 25)
Updated MSM SRAM data (Page 28)
Updated the C66x CorePac Block Diagram (Page 24)
Revision C
Added a footnote to the System Event Mapping table (Page 113)
354 Revision History
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback