TCI6636K2H Datasheet, PDF (293/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Figure 10-7 Main PLL and PLL Controller
TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
SYSCLK(N|P)
ALTCORECLK(N|P)
CORECLKSEL
PLLM
PLL
PLLD
VCO
0
CLKOD
1
BYPASS
PLLOUT
PLL Controller
POSTDIV
/1
PLLDIV1
/1
PLLDIV2
/x
PLLDIV3
/z
PLLDIV4
SYSCLK1
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
C66x
CorePacs
To Peripherals,
HyperLink, etc.
To Switch Fabric,
Accelerators, SRIO,
SmartReflex, etc.
Note that the Main PLL Controller registers can be accessed by any master in the device. The PLLM[5:0] bits of the
multiplier are controlled by the PLLM Register inside the PLL Controller and the PLLM[12:6] bits are controlled by
the chip-level MAINPLLCTL0 Register. The output divide and bypass logic of the PLL are controlled by fields in the
SECCTL Register in the PLL Controller. Only PLLDIV3, and PLLDIV4 are programmable on the device. See the
Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide in section 2.4 ‘‘Related Documentation from
Texas Instruments’’ on page 19for more details on how to program the PLL controller.
The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are
determined by a combination of this PLL and the Main PLL Controller. The Main PLL Controller also controls reset
propagation through the chip, clock alignment, and test points. The Main PLL Controller monitors the PLL status
and provides an output signal indicating when the PLL is locked.
Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone II Devices (in development)
for detailed recommendations. For the best performance, TI recommends that all the PLL external components be
on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL
jitter, maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the EMI
Filter).
The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see
Section 10.5.5 ‘‘Main PLL Controller/ARM/SRIO/HyperLink/PCIe/USB Clock Input Electrical Data/Timing’’.
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback
TCI6636K2H Peripheral Information and Electrical Specifications 293