TCI6636K2H Datasheet, PDF (238/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2.3.1 Device Status (DEVSTAT) Register
The Device Status Register depicts device configuration selected upon a power-on reset by the POR or RESETFULL
pin. Once set, these bits remain set until a power-on reset. The Device Status Register is shown in the figure below.
Figure 8-13 Device Status Register
31
26
25
24
22
21
Reserved
DDR3A_MAP_EN
Reserved
ARMAVSSHARED
R-0000 0000 0000 00
R-x
R-x
R/W-x
spacer
20
19
18
17
16
1
Reserved
MAINPLLODSEL
AVSIFSEL
BOOTMODE
R-x
R/W-x
R/W-xx
R/W-x xxxx xxxx xxxx xxx
Legend: R = Read only; RW = Read/Write; -n = value after reset
1 x indicates the bootstrap value latched via the external pin
0
LENDIAN
R-x ⁽¹⁾
Table 8-31 Device Status Register Field Descriptions
Bit
31-26
25
Field
Reserved
DDR3A_MAP_EN
24-22 Reserved
21 ARMAVSSHARED
20 Reserved
19 MAINPLLODSEL
18-17 AVSIFSEL
16-1 BOOTMODE
0
LENDIAN
End of Table 8-31
Description
Reserved. Read only, writes have no effect.
DDR3A mapping enable
0 = DDR3A memory is accessible from ARM at 0x8:0000_0000 - 0x9:FFFF_FFFF.
1 = DDR3A memory is accessible in 32b space from ARM, i.e., at 0x0:8000_0000 - 0x0:FFFF_FFFF. DDR3A is also
accessible at 0x8:0000_0000 - 0x9:FFFF_FFFF, with the space 0x0:8000_0000 - 0x0:FFFF_FFFF address aliased at
0x8:0000_0000 - 0x8:7FFF_FFFF.
Reserved
ARM AVS Shared with the rest of SOC AVS
0 = Reserved
1 = ARM Core voltage and rest of SoC core voltage share
Reserved
Main PLL Output divider select
0 = Main PLL output divider needs to be set to 2 by BOOTROM
1 = Reserved
AVS interface selection
00 - AVS 4pin 6bit Dual-Phase VCNTL[5:2] (Default)
01 - AVS 4pin 4bit Single-Phase VCNTL[5:2]
10 - AVS 6pin 6bit Single-Phase VCNTL[5:0]
11 - I²C
Determines the bootmode configured for the device. For more information on bootmode, see Section 8.1.2 ‘‘Boot
Modes Supported’’ on page 209 and see the Bootloader for the C66x DSP User Guide in2.4 ‘‘Related Documentation from
Texas Instruments’’ on page 19.
Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian mode or little
endian mode (default).
0 = System is operating in big endian mode
1 = System is operating in little endian mode (default)
238 Device Boot and Configuration
Copyright 2013 Texas Instruments Incorporated
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