TCI6636K2H Datasheet, PDF (329/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-48 MACID2 Register Field Descriptions (Part 2 of 2)
Bit
Field
Description
16
BCAST
Default m/b-cast reception
0 = Broadcast
1 = Disabled
15-0 MAC ID
End of Table 10-48
MAC ID. Upper 16 bits.
There is a central processor time synchronization (CPTS) submodule in the Ethernet switch module that can be used
for time synchronization. Programming this register selects the clock source for the CPTS_RCLK. See the Gigabit
Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas
Instruments’’ on page 19for the register address and other details about the time synchronization submodule. The
register CPTS_RFTCLK_SEL for reference clock selection of the time synchronization submodule is shown in
Figure 10-48.
Figure 10-48 RFTCLK Select Register (CPTS_RFTCLK_SEL)
31
4
3
0
Reserved
CPTS_RFTCLK_SEL
R-0
RW - 0
Legend: R = Read only; -x, value is indeterminate
Table 10-49 RFTCLK Select Register Field Descriptions
Bit
Field
Description
31-4 Reserved
Reserved. Read as 0.
3-0
CPTS_RFTCLK_SEL
End of Table 10-49
Reference clock select. This signal is used to control an external multiplexer that selects one of 8 clocks for time sync
reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is cleared to 0 in the
TS_CTL register.
0000 = SYSCLK2
0001 = SYSCLK3
0010 = TIMI0
0011 = TIMI1
1000 = TSREFCLK
Others = Reserved
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TCI6636K2H Peripheral Information and Electrical Specifications 329