TCI6636K2H Datasheet, PDF (48/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 5-2
Terminal Functions — Signals and Control by Function (Part 11 of 19)
Signal Name
Ball No. Type IPD/IPU Description
DDR3BCLKOUTP0
DDR3BCLKOUTN0
AD38 OZ
AD39 OZ
DDR3B EMIF output clocks to drive SDRAM (one clock pair for Rank0)
DDR3BCLKOUTP1
DDR3BCLKOUTN1
AC39 OZ
AC38 OZ
DDR3B EMIF output clocks to drive SDRAM (one clock pair for Rank1)
DDR3BODT0
AC33 OZ
DDR3B EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3BODT1
AD34 OZ
DDR3B EMIF on-die termination outputs used to set termination on the SDRAMs
DDR3BRESET
AC32 OZ
DDR3B reset signal
DDR3BRZQ0
AA31 A
PTV compensation pin for DDR3B
DDR3BRZQ1
P32
A
PTV compensation pin for DDR3B
DDR3BRZQ2
AK32 A
PTV compensation pin for DDR3B
EMIF16
EMIFBE0
H34
O Up
EMIFBE1
H33
O Up
EMIFCE0
G33
O Up
EMIFCE1
G32
O Up
EMIFCE2
G34
O Up
EMIFCE3
E36
O Up
EMIF control signals
EMIFOE
E37
O Up
EMIFRW
F33
O Up
EMIFWAIT0
E38
I
Down
EMIFWAIT1
D39
I
Down
EMIFWE
F36
O Up
EMIFA00
F34
O Down
EMIFA01
F37
O Down
EMIFA02
G36
O Down
EMIFA03
E39
O Down
EMIFA04
E34
O Down
EMIFA05
J34
O Down
EMIFA06
H35
O Down
EMIFA07
EMIFA08
K33
O Down
EMIF address
C35
O Down
EMIFA09
G37
O Down
EMIFA10
F38
O Down
EMIFA11
D35
O Down
EMIFA12
H36
O Down
EMIFA13
E35
O Down
EMIFA14
G38
O Down
EMIFA15
F39
O Down
48 Terminals
Copyright 2013 Texas Instruments Incorporated
Submit Documentation Feedback