TCI6636K2H Datasheet, PDF (255/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2.3.20 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
The registers defined in ARM Configuration Register 0 (ARMENDIAN_CFGr_0) and ARM Configuration
Register 1 (ARMENDIAN_CFGr_1) control the way Cortex-A15 processor core access to peripheral MMRs shows
up in the Cortex-A15 processor registers. The purpose is to provide an endian-invariant view of the peripheral
MMRs when performing a 32-bit access. (Only one of the eight register sets is shown.)
Figure 8-31 ARM Endian Configuration Register 0 (ARMENDIAN_CFGr_0), r=0..7
31
87
0
BASEADDR
Reserved
RW-0000 0000 0000 0000 0000 0000
R-0000 0000
Legend: RW = Read/Write; -n = value after reset
Table 8-49 ARM Endian Configuration Register 0 Field Descriptions
Bit Field
31-8 BASEADDR
7-0 Reserved
End of Table 8-49
Description
24-bit Base Address of Configuration Region R
This base address defines the start of a contiguous block of Memory Mapped Register space for which a word swap is
done by the ARM CorePac bridge.
Reserved
8.2.3.21 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
Figure 8-32 ARM Endian Configuration Register 1 (ARMENDIAN_CFGr_1), r=0..7
31
43
0
Reserved
SIZE
R-0000 0000 0000 0000 0000 0000 0000
RW-0000
Legend: RW = Read/Write; -n = value after reset
Table 8-50 ARM Endian Configuration Register 1 Field Descriptions
Bit Field
31-4 Reserved
3-0 SIZE
End of Table 8-50
Description
Reserved
4-bit encoded size of Configuration Region R
The value in the SIZE field defines the size of the contiguous block of Memory Mapped Register space for which a
word swap is done by the ARM CorePac bridge (starting from ARMENDIAN_CFGr_0.BASEADDR).
0000 : 64KB
0001 : 128KB
0010 : 256KB
0011 : 512KB
0100 : 1MB
0101 : 2MB
0110 : 4MB
0111 : 8MB
1000 : 16MB
1001 : 32MB
1010 : 64MB
1011 : 128MB
Others : Reserved
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