TCI6636K2H Datasheet, PDF (353/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.36.7.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the TCI6636K2H device includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the device’s internal emulation logic will always be properly
initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high.
However, some third-party JTAG controllers may not drive TRST high, but expect the use of an external pullup
resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and
externally drive TRST high before attempting any emulation or boundary scan operations.
10.36.7.2 JTAG Electrical Data/Timing
Table 10-70 JTAG Test Port Timing Requirements
(see Figure 10-63)
No.
1
t_c(TCK)
1a tw(TCKH)
Cycle time, TCK
Pulse duration, TCK high (40% of tc)
1b tw(TCKL)
Pulse duration, TCK low(40% of tc)
3 tsu(TDI-TCK)
Input setup time, TDI valid to TCK high
3 tsu(TMS-TCK)
Input setup time, TMS valid to TCK high
4 th(TCK-TDI)
Input hold time, TDI valid from TCK high
4 th(TCK-TMS)
End of Table 10-70
Input hold time, TMS valid from TCK high
Min
Max Unit
23
ns
9.2
ns
9.2
ns
2
ns
2
ns
10
ns
10
ns
Table 10-71 JTAG Test Port Switching Characteristics
(see Figure 10-63)
No.
Parameter
2
t_d(TCKL-TDOV)
End of Table 10-71
Delay time, TCK low to TDO valid
Figure 10-63 JTAG Test-Port Timing
1
1a
1b
TCK
2
TDO
4
3
TDI / TMS
Min
Max Unit
8.24 ns
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TCI6636K2H Peripheral Information and Electrical Specifications 353