TCI6636K2H Datasheet, PDF (31/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
4.3.3 ARM Interrupt Controller
The ARM CorePac interrupt controller (AINTC) is responsible for prioritizing all service requests from the system
peripherals and the Secondary interrupt controller CIC2 and then generating either nIRQ or nFIQ to the
Cortex-A15 processor. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are
programmable. The AINTC interfaces to the Cortex-A15 processor via the AXI port through an VBUS2AXI bridge
and runs at half the processor speed. It has the capability to handle up to 480 requests, which can be
steered/prioritized as A15 nFIQ or nIRQ interrupt requests.
The general features of the AINTC are:
• Up to 480 level sensitive shared peripheral interrupts (SPI) inputs
• Individual priority for each interrupt input
• Each interrupt can be steered to nFIQ or nIRQ
• Independent priority sorting for nFIQ and nIRQ
• Secure mask flag
On the chip level, there is a dedicated chip level interrupt controller to serve the ARM interrupt controller. See the
Interrupt section for more details.
The figure below shows an overall view of the ARM CorePac Interrupt Controller.
Figure 4-2 ARM Interrupt Controller for Four Cortex-A15 Processor Cores
Peripherals
CIC2
480 SPI
Interrupts
ARM INTC
Generic
Interrupt
Controller
400
FIQ, IRQ,
Virtual FIQ,
Virtual IRQ
16 PPIs
CPU/6 Clock
GTB Counter Clock
Power On Reset
Global
Time Base
Counter
64 Bits
Cortex
A15
VBUSP Interface
VBUSP2AXI
Bridge
16 Software
Generated
Inputs
4.3.4 Endianess
The ARM CorePac can operate in either little endian or big endian mode. When the ARM CorePac is in little endian
mode and the rest of the system is in big endian mode, the bridges in the ARM CorePac are responsible for
performing the endian conversion.
4.4 CFG Connection
The ARM CorePac has two slave ports. The TCI6636K2H masters cannot access the ARM CorePac internal memory
space.
1. Slave port 0 (TeraNet 3P_A) is a 32 bit wide port used for the ARM Trace module.
2. Slave port 1 (TeraNet 3P_B) is a 32 bit wide port used to access the rest of the system configuration.
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