TCI6636K2H Datasheet, PDF (301/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-21 Reset Type Status Register Field Descriptions
Bit Field
Description
31-29 Reserved
Reserved. Always reads as 0. Writes have no effect.
28 EMU-RST
Reset initiated by emulation
0 = Not the last reset to occur
1 = The last reset to occur
27-12 Reserved
Reserved. Always reads as 0. Writes have no effect.
11 WDRST3
10 WDRST2
9
WDRST1
8
WDRST0
Reset initiated by Watchdog Timer[N]
0 = Not the last reset to occur
1 = The last reset to occur
7-3 Reserved
Reserved. Always reads as 0. Writes have no effect.
2
PLLCTLRST
Reset initiated by PLLCTL
0 = Not the last reset to occur
1 = The last reset to occur
1
RESET
RESET reset
0 = RESET was not the last reset to occur
1 = RESET was the last reset to occur
0
POR
End of Table 10-21
Power-on reset
0 = Power-on reset was not the last reset to occur
1 = Power-on reset was the last reset to occur
10.5.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value
is 0x5A69. A valid key will be stored as 0x000C. Any other key value is invalid. When the RSTCTRL or the RSTCFG
is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register
(RSTCTRL) is shown in Figure 10-14 and described in Table 10-22.
Figure 10-14 Reset Control Register (RSTCTRL)
31
17
16
15
0
Reserved
R-0x0000
SWRST
R/W-0x ⁽¹⁾
KEY
R/W-0x0003
Legend: R = Read only; -n = value after reset;
1 Writes are conditional based on valid key.
Table 10-22 Reset Control Register Field Descriptions
Bit Field
Description
31-17 Reserved
Reserved
16 SWRST
Software reset
0 = Reset
1 = Not reset
15-0 KEY
End of Table 10-22
Key used to enable writes to RSTCTRL and RSTCFG.
Copyright 2013 Texas Instruments Incorporated
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TCI6636K2H Peripheral Information and Electrical Specifications 301