TCI6636K2H Datasheet, PDF (174/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 6-30 IPC Generation Registers (IPCGRx) (Part 2 of 2)
Address Start
Address End
Size
Register Name
0x026202A4
0x026202A7
4B
IPCAR9
0x026202A8
0x026202AB
4B
IPCAR10
0x026202AC
0x026202AF
4B
IPCAR11
0x026202B0
0x026202BB
12B
Reserved
0x026202A0
0x026202BB
28B
Reserved
0x026202BC
End of Table 6-30
0x026202BF
4B
IPCARH
Description
IPC Acknowledgement Register for ARM CorePac1
IPC Acknowledgement Register for ARM CorePac2
IPC Acknowledgement Register for ARM CorePac3
Reserved
Reserved
IPC Acknowledgement Register for host
6.3.4 NMI and LRESET
The Non-Maskable Interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One
NMI pin and one LRESET pin are shared by all eight C66x CorePacs on the device. The CORESEL[3:0] pins can be
configured to select between the eight C66x CorePacs available as shown in Table 6-31.
Table 6-31 LRESET and NMI Decoding (Part 1 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
XXXX
X
X
1
No local reset or NMI assertion
0000
0
X
0
Assert local reset to C66x CorePac0
0001
0
X
0
Assert local reset to C66x CorePac1
0010
0
X
0
Assert local reset to C66x CorePac2
0011
0
X
0
Assert local reset to C66x CorePac3
0100
0
X
0
Assert local reset to C66x CorePac4
0101
0
X
0
Assert local reset to C66x CorePac5
0110
0
X
0
Assert local reset to C66x CorePac6
0111
0
X
0
Assert local reset to C66x CorePac7
1XXX
0
X
0
Assert local reset to all C66x CorePacs
0000
1
1
0
De-assert local reset & NMI to C66x CorePac0
0001
1
1
0
De-assert local reset & NMI to C66x CorePac1
0010
1
1
0
De-assert local reset & NMI to C66x CorePac2
0011
1
1
0
De-assert local reset & NMI to C66x CorePac3
0100
1
1
0
De-assert local reset & NMI to C66x CorePac4
0101
1
1
0
De-assert local reset & NMI to C66x CorePac5
0110
1
1
0
De-assert local reset & NMI to C66x CorePac6
0111
1
1
0
De-assert local reset & NMI to C66x CorePac7
1XXX
1
1
0
De-assert local reset & NMI to all C66x CorePacs
0000
1
0
0
Assert NMI to C66x CorePac0
0001
1
0
0
Assert NMI to C66x CorePac1
0010
1
0
0
Assert NMI to C66x CorePac2
0011
1
0
0
Assert NMI to C66x CorePac3
0100
1
0
0
Assert NMI to C66x CorePac4
0101
1
0
0
Assert NMI to C66x CorePac5
0110
1
0
0
Assert NMI to C66x CorePac6
174 Memory, Interrupts, and EDMA for TCI6636K2H
Copyright 2013 Texas Instruments Incorporated
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