TCI6636K2H Datasheet, PDF (233/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
8.2 Device Configuration
Certain device configurations like boot mode and endianess are selected at device power-on reset. The status of the
peripherals (enabled/disabled) is determined after device power-on reset. By default, the peripherals on the device
are disabled and need to be enabled by software before being used.
8.2.1 Device Configuration at Device Reset
The logic level present on each device configuration pin is latched at power-on reset to determine the device
configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors
or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The device
configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid
contention, the control device must stop driving the device configuration pins of the DSP. Table 8-29 describes the
device configuration pins.
Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state),
the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an
external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and
situations in which external pullup/pulldown resistors are required, see the Pullup/PullDown Resistors
section of the Terminals chapter.
Table 8-29 Device Configuration Pins
Configuration Pin
LENDIAN^{(1) (2)}
BOOTMODE[15:0] ^{(1) (2)}
AVSIFSEL[1:0] ^{(1) (2)}
MAINPLLODSEL ^{(1) (2)}
ARMAVSSHARED⁽¹⁾
BOOTMODE_RSVD⁽¹⁾
DDR3A_MAP_EN⁽¹⁾
Pin No.
F29
B31, E32, A31,
F30, E30, F31, G30,
A30, C30, D30,
E29, B29, A35,
D29, B30, F29
M1, M2
E32
G24
B31
A36
IPD/IPU ⁽¹⁾
IPU
IPD
IPD
IPD
IPD
IPD
IPD
Description
Device endian mode (LENDIAN)
0 = Device operates in big endian mode
1 = Device operates in little endian mode
Method of boot
See ‘‘Boot Modes Supported’’ on page 209 for more details.
See the Bootloader for the C66x DSP User Guide in 2.4 ‘‘Related Documentation from Texas
Instruments’’ on page 19for detailed information on boot configuration.
AVS interface selection
00 = AVS 4-pin 6-bit Dual-Phase VCNTL[5:2] (Default)
01 = AVS 4-pin 4-bit Single-Phase VCNTL[5:2]
10 = AVS 6-pin 6-bit Single-Phase VCNTL[5:0]
11 = I²C
Main PLL Output divider select
0 = Main PLL output divider needs to be set to 2 by BOOTROM
1 = Reserved
ARM AVS Shared with the rest of SOC AVS
0 = Reserved
1 = ARM Core voltage and rest of SoC core voltage shared
Boot mode reserved. Pulldown resistor required on pin.
Control ARM remapping of DDR3A address space in the lower 4GB (32b space) Mode select
0 = DDR3A memory is accessible from ARM at 0x08 0000 0000 - 0x09 FFFF FFFF.
1 = DDR3A memory is accessible from ARM at 0x00 8000 0000 - 0x00 FFFF FFFF
with 0x00 8000 0000 - 0x00 FFFF FFFF aliased at 0x08 0000 0000 - 0x08 7FFF FFFF.
End of Table 8-29
1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on
pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see the Pullup/Pulldown Resistors section of the Terminals chapter.
2 These signal names are the secondary functions of these pins.
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Device Boot and Configuration 233