TCI6636K2H Datasheet, PDF (324/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.12 HyperLink Peripheral
The TCI6636K2H includes HyperLinks for companion device interfaces. This is a four-lane SerDes interface
designed to operate at up to 10 Gbps per lane from pin-to-pin. The interface is used to connect with external
accelerators that are manufactured using TI libraries. The HyperLink lines must be connected with DC coupling.
The interface includes the serial station management interfaces used to send power management and flow messages
between devices. Each HyperLink interface consists of four LVCMOS inputs and four LVCMOS outputs configured
as two 2-wire input buses and two 2-wire output buses. Each 2-wire bus includes a data signal and a clock signal.
Table 10-43 HyperLink Peripheral Timing Requirements
(see Figure 10-39, Figure 10-40 and Figure 10-41)
No.
FL Interface
1 tc(HYPTXFLCLK)
Clock period - HYPTXFLCLK (C1)
2 tw(HYPTXFLCLKH)
High pulse width - HYPTXFLCLK
3 tw(HYPTXFLCLKL)
Low pulse width - HYPTXFLCLK
6 tsu(HYPTXFLDAT-HYPTXFLCLKH)
Setup time - HYPTXFLDAT valid before HYPTXFLCLK high
7 th(HYPTXFLCLKH-HYPTXFLDAT)
Hold time - HYPTXFLDAT valid after HYPTXFLCLK high
6 tsu(HYPTXFLDAT-HYPTXFLCLKL)
Setup time - HYPTXFLDAT valid before HYPTXFLCLK low
7 th(HYPTXFLCLKL-HYPTXFLDAT)
Hold time - HYPTXFLDAT valid after HYPTXFLCLK low
PM Interface
1 tc(HYPRXPMCLK)
Clock period - HYPRXPMCLK (C3)
2 tw(HYPRXPMCLK)
High pulse width - HYPRXPMCLK
3 tw(HYPRXPMCLK)
Low pulse width - HYPRXPMCLK
6 tsu(HYPRXPMDAT-HYPRXPMCLKH) Setup time - HYPRXPMDAT valid before HYPRXPMCLK high
7 th(HYPRXPMCLKH-HYPRXPMDAT)
Hold time - HYPRXPMDAT valid after HYPRXPMCLK high
6 tsu(HYPRXPMDAT-HYPRXPMCLKL) Setup time - HYPRXPMDAT valid before HYPRXPMCLK low
7 th(HYPRXPMCLKL-HYPRXPMDAT)
End of Table 10-43
Hold time - HYPRXPMDAT valid after HYPRXPMCLK low
Min Max Unit
5.75
ns
0.4*C1 0.6*C1 ns
0.4*C1 0.6*C1 ns
1
ns
1
ns
1
ns
1
ns
5.75
ns
0.4*C3 0.6*C3 ns
0.4*C3 0.6*C3 ns
1
ns
1
ns
1
ns
1
ns
Table 10-44 HyperLink Peripheral Switching Characteristics (Part 1 of 2)
(see Figure 10-39, Figure 10-40 and Figure 10-41)
No.
Parameter
FL Interface
1 tc(HYPRXFLCLK)
Clock period - HYPRXFLCLK (C2)
2 tw(HYPRXFLCLKH)
High pulse width - HYPRXFLCLK
3 tw(HYPRXFLCLKL)
Low pulse width - HYPRXFLCLK
4 tosu(HYPRXFLDAT-HYPRXFLCLKH) Setup time - HYPRXFLDAT valid before HYPRXFLCLK high
5 toh(HYPRXFLCLKH-HYPRXFLDAT)
Hold time - HYPRXFLDAT valid after HYPRXFLCLK high
4 tosu(HYPRXFLDAT-HYPRXFLCLKL)
Setup time - HYPRXFLDAT valid before HYPRXFLCLK low
5 toh(HYPRXFLCLKL-HYPRXFLDAT)
Hold time - HYPRXFLDAT valid after HYPRXFLCLK low
PM Interface
1 tc(HYPTXPMCLK)
Clock period - HYPTXPMCLK (C4)
2 tw(HYPTXPMCLK)
High pulse width - HYPTXPMCLK
3 tw(HYPTXPMCLK)
Low pulse width - HYPTXPMCLK
4 tosu(HYPTXPMDAT-HYPTXPMCLKH) Setup time - HYPTXPMDAT valid before HYPTXPMCLK high
Min
Max
Unit
6.4
0.4*C2
0.4*C2
0.25*C2-0.4
0.25*C2-0.4
0.25*C2-0.4
0.25*C2-0.4
ns
0.6*C2 ns
0.6*C2 ns
ns
ns
ns
ns
6.4
0.4*C4
0.4*C4
0.25*C2-0.4
ns
0.6*C4 ns
0.6*C4 ns
ns
324 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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