TCI6636K2H Datasheet, PDF (300/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 10-19 PLLDIV Divider Ratio Change Status Register Field Descriptions
Bit
Field
Description
31-5
Reserved
2-0
Reserved. This bit location is always read as 0. A value written to this field has no effect.
4
SYS4
3
SYS3
End of Table 10-19
Identifies when the SYSCLKn divide ratio has been modified.
0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
10.5.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK Status Register (SYSTAT) shows the status of SYSCLK[4:1]. SYSTAT is shown in Figure 10-12 and
described in Table 10-20.
Figure 10-12 SYSCLK Status Register (SYSTAT)
31
Reserved
R-n
Legend: R/W = Read/Write; R = Read only; -n = value after reset
4
3
2
1
0
SYS4ON SYS3ON SYS2ON SYS1ON
R-1
R-1
R-1
R-1
Table 10-20 SYSCLK Status Register Field Descriptions
Bit
Field
Description
31-4 Reserved
3-0
SYS[N ⁽¹⁾]ON
End of Table 10-20
Reserved. This location is always read as 0. A value written to this field has no effect.
SYSCLK[N] on status
0 = SYSCLK[N] is gated
1 = SYSCLK[N] is on
1 Where N = 1, 2, 3, or 4
10.5.2.6 Reset Type Status Register (RSTYPE)
The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in
Figure 10-13 and described in Table 10-21.
Figure 10-13 Reset Type Status Register (RSTYPE)
31
29
28
27
12
11
8
7
3
2
1
0
Reserved
EMU-RST
Reserved
WDRST[N]
Reserved
PLLCTRLRST RESET
POR
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Legend: R = Read only; -n = value after reset
300 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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