TCI6636K2H Datasheet, PDF (217/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
Table 8-9
NAND Boot Device Configuration Field Descriptions
Bit
Field
Description
16
Boot Devices
Boot Devices[16] used conjunction with Boot Devices [3-1]
0 = Other boot modes
1 = NAND boot mode
15-13 First Block
First Block. This value is used to calculate the first block read. The first block read is the first block value *16.
12
Clear
ClearNAND
0 = Device is not a ClearNAND (default)
1 = Device is a ClearNAND
11-9 Chip Sel/ARM PLL
Setting
When Boot Master = 0 (ARM is Boot Master), Pin[11:9] used as ARM PLL Setting and the chip select region CS2 is
used. The PLL default settings are determined by the [11:9] bits. This will set the PLL to the maximum clock setting
for the device. Table 8-27 shows settings for various input clock frequencies.
When Boot Master =1 (C66x is Boot Master), Pin[10:9] used as Chip Sel that specifies the chip select region,
CS2-CS5.
00 = CS2
01 = CS3
10 = CS4
11 = CS5
8
Boot Master
Boot Master select
0 = ARM is boot master (default)
1 = C66x is boot master
7-5
SYS PLL Setting
The PLL default settings are determined by the [7:5] bits. This will set the PLL to the maximum clock setting for the
device. Table 8-27 shows settings for various input clock frequencies.
4
Min
Minimum boot pin select. When Min is 1, it means that the BOOTMODE [15:3] pins are don't cares. Only
BOOTMODE [2:0] pins (DEVSTAT[3:1]) will determine boot. Default values are assigned to values that would
normally be set by the other BOOTMODE pins when Min is 0.
0 = Minimum boot pin select disabled
1 = Minimum boot pin select enabled.
3-1
Boot Devices
Boot Devices
011 = NAND boot mode
Others = Other boot modes
0
Lendian
End of Table 8-9
Endianess
0 = Big endian
1 = Little endian
8.1.2.2.6 Serial Rapid I/O Boot Device Configuration
The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.
Figure 8-8 Serial Rapid I/O Boot Device Configuration Fields
16
X
Lane
15 14
Ref Clock
Ref Clock
13 12
Data Rate
Data Rate
DEVSTAT Boot Mode Pins ROM Mapping
11 10 9
8
765
Lane Setup
Boot Master=1
Sys PLL Cfg
ARM PLL Cfg
Boot Master=0
Sys PLL Cfg
4 321
Min
100
Min
100
0
Lendian
Lendian
Copyright 2013 Texas Instruments Incorporated
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Device Boot and Configuration 217