TCI6636K2H Datasheet, PDF (326/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
10.13 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the device and a
UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550
asynchronous communications element which, in turn, is a functional upgrade of the TL16C450. Functionally
similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate
FIFO (TL16C550) mode. This relieves the C66x of excessive software overhead by buffering received and
transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of
error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial
conversion on data received from the C66x CorePac to be sent to the peripheral device. The C66x CorePac can read
the UART status at any time. The UART includes control capability and a processor interrupt system that can be
tailored to minimize software management of the communications link. For more information on UART, see the
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide in 2.4 ‘‘Related
Documentation from Texas Instruments’’ on page 19.
Table 10-45 UART Timing Requirements
(see Figure 10-42 and Figure 10-43)
No.
Receive Timing
4 tw(RXSTART)
Pulse width, receive start bit
5 tw(RXH)
Pulse width, receive data/parity bit high
5 tw(RXL)
Pulse width, receive data/parity bit low
6 tw(RXSTOP1)
Pulse width, receive stop bit 1
6 tw(RXSTOP15)
Pulse width, receive stop bit 1.5
6 tw(RXSTOP2)
Pulse width, receive stop bit 2
Autoflow Timing Requirements
8 td(CTSL-TX)
End of Table 10-45
Delay time, CTS asserted to START bit transmit
1 U = UART baud time = 1/programmed baud rate
2 P = 1/(SYSCLK1/6)
Figure 10-42 UART Receive Timing Waveform
4
5
5
RXD
Stop/Idle
Start
Bit 0
Bit 1
Bit N-1 Bit N
Parity
Min
Max
Unit
0.96U ⁽¹⁾
0.96U
0.96U
0.96U
0.96U
0.96U
1.05U ns
1.05U ns
1.05U ns
1.05U ns
1.05U ns
1.05U ns
P ⁽²⁾
5P ns
6
Stop
Idle
Start
Figure 10-43 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
8
TXD
Bit N-1 Bit N
Stop
Start
Bit 0
CTS
326 TCI6636K2H Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
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