TCI6636K2H Datasheet, PDF (176/362 Pages) Texas Instruments – Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

TCI6636K2H
Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
SPRS835F—October 2013
• 64 DMA channels for all EDMA3CC
– Manually triggered (CPU writes to channel controller register)
– External event triggered
– Chain triggered (completion of one transfer triggers another)
• 8 Quick DMA (QDMA) channels per EDMA3CCx
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0,
EDMA3CC3, and EDMA3CC4
• Four transfer controllers and four event queues with programmable system-level priority each for DMA3CC1
and EDMA3CC2
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
6.4.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases. For most applications, increment mode can be used.
On the TCI6636K2H SoC, the EDMA can use constant addressing mode only with the enhanced Viterbi decoder
coprocessor (VCP) and the enhanced turbo decoder coprocessor (TCP). Constant addressing mode is not supported
by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all peripherals,
including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct Memory
Access 3 (EDMA3) for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas Instruments’’ on
page 19.
For the range of memory addresses that includes EDMA3 channel controller (EDMA3CC) control registers and
EDMA3 transfer controller (TPTC) control registers see Section 6.1 ‘‘Memory Map Summary’’ on page 81. For
memory offsets and other details on EDMA3CC and TPTC Control Register entries, see the Enhanced Direct
Memory Access 3 (EDMA3) for KeyStone Devices User Guide in 2.4 ‘‘Related Documentation from Texas
Instruments’’ on page 19.
6.4.2 EDMA3 Channel Controller Configuration
Table 6-32 shows the configuration for each of the EDMA3 channel controllers present on the device.
Table 6-32 EDMA3 Channel Controller Configuration
Description
EDMA3 CC0
Number of DMA channels in channel controller
64
Number of QDMA channels
8
Number of interrupt channels
64
Number of PaRAM set entries
512
Number of event queues
2
Number of transfer controllers
2
Memory protection existence
Yes
Number of memory protection and shadow regions
8
End of Table 6-32
EDMA3 CC1
64
8
64
512
4
4
Yes
8
EDMA3 CC2
64
8
64
512
4
4
Yes
8
EDMA3 CC3
64
8
64
512
2
2
Yes
8
EDMA3 CC4
64
8
64
512
2
2
Yes
8
176 Memory, Interrupts, and EDMA for TCI6636K2H
Copyright 2013 Texas Instruments Incorporated
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